1. Field of the Invention
The present invention is related to a semiconductor designing apparatus for designing a semiconductor circuit.
2. Description of the Related Art
Conventionally, in the case that layout designing operations as to semiconductor memory circuits and semiconductor analog circuits are carried out, the designing operations have been semi-automatically performed in a manual manner. FIG. 25 is a block diagram for schematically indicating an arrangement of a conventional semiconductor designing apparatus. The conventional semiconductor designing apparatus shown in this drawing employs such a method that a layout designing operation is carried out by a layout editing unit 5 based upon net list information of a circuit diagram and layout information.
In FIG. 25, reference numeral 1 shows an input unit; reference numeral 2 indicates a CPU for processing data based upon information entered from the input unit 1; reference numeral 3 represents a circuit editing unit for executing a circuit editing operation with respect to the input data processed by the CPU 2; reference numeral 4 indicates a circuit diagram database into which circuit diagrams used by the circuit editing unit 3 have been stored; reference numeral 5 shows a layout editing unit for executing a layout editing operation with respect to input data processed by the CPU 2; and reference numeral 6 shows a layout database into which layouts used by the layout editing unit 5 have been stored. Also, reference numeral 7 shows a design rule judging unit for checking a design rule of a layout formed by the layout editing unit 5; reference numeral 8 represents a connect extracting unit for extracting connection information of both layout data of the layout editing unit 5 and circuit data of the circuit editing unit 3; and reference numeral 9 shows an output unit for outputting a result obtained by the CPU 2.
In this case, FIG. 26 is a circuit diagram of a gate level. In FIG. 26, symbol “IG1” shows a 2-input NOR, symbols “a1” and “a2” represent inputs, and symbol “b1” indicates an output. Symbol “IG2” shows a 2-input NAND, symbols “b1” and “b2” indicate inputs, and symbol “c1” represents an output. Symbol “IG3” denotes an inverter, symbol “c1” shows an input, and symbol “c2” indicates an output.
FIG. 27 is a circuit diagram of a transistor level. In FIG. 27, symbol “IT1” shows a 2-input NOR, symbols “a1” and “a2” represent inputs, and symbol “b1” indicates an output. In the transistor level, the 2-input NOR IT1 is constituted of PMOS transistors pa1 and pa2, and NMOS transistors na1 and na2; symbol “a1” is connected to a gate of the PMOS transistor pa1, symbol “a3” is connected to a source thereof, and symbol “b1” is connected to a drain thereof; symbol “a2” is connected to a gate of the PMOS transistor pa2, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “a3” is connected to a drain thereof; symbol “a1” is connected to a gate of the NMOS transistor na1, symbol “vss (ground potential)” is connected to a source thereof, symbol “b1” is connected to a drain thereof; and symbol “a2” is connected to a gate of the NMOS transistor na2, symbol “vss (ground potential)” is connected to a source thereof, and an symbol “b1” is connected to a drain thereof.
Symbol “IT2” shows a 2-input NAND, symbols “b1” and “b2” represent inputs, and symbol “c1” indicates an output. In the transistor level, the 2-input NAND IT2 is constituted by PMOS transistors pb1 and pb2, and NMOS transistors nb1 and nb2; symbol “b1” is connected to a gate of the PMOS transistor pb1, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c1” is connected to a drain thereof; symbol “b2” is connected to a gate of the PMOS transistor pa2, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c1” is connected to a drain thereof; symbol “b1” is connected to a gate of the NMOS transistor nb1, symbol “b3” is connected to a source thereof, symbol “c1” is connected to a drain thereof; and symbol “b2” is connected to a gate of the NMOS transistor nb2, symbol “vss (ground potential)” is connected to a source thereof, and symbol “b3” is connected to a drain thereof.
Symbol “IT3” shows an inverter, symbol “c1” indicates an input, and symbol “c2” represents an output. In the transistor level, the inverter IT3 is constructed of a PMOS transistor pc1 and an NMOS transistor nc1. Symbol “c1” is connected to a gate of the PMOS transistor pc1, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c2” is connected to a drain thereof; symbol “c1” is connected to a gate of the NMOS transistor nc1, symbol “vss (ground potential)” is connected to a source thereof, and symbol “c2” is connected to a drain thereof.
FIG. 28 is a structural diagram of a layout of a transistor level. In FIG. 28, this layout is constituted by PMOS transistors pa1, pa2, pb1, pb2, pc1, and NMOS transistors na1, na2, nb1, nb2, nc1. Symbol “a1” is connected to a gate of the PMOS transistor pa1, symbol “a3” is connected to a source thereof, and symbol “b1” is connected to a drain thereof; symbol “a2” is connected to a gate of the PMOS transistor pa2, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “a3” is connected to a drain thereof; symbol “a1” is connected to a gate of the NMOS transistor na1, symbol “vss (ground potential)” is connected to a source thereof, symbol “b1” is connected to a drain thereof; symbol “a2” is connected to a gate of the NMOS transistor na2, symbol “vss (ground potential)” is connected to a source thereof, and an symbol “b1” is connected to a drain thereof. Symbol “b1” is connected to a gate of the PMOS transistor pb1, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c1” is connected to a drain thereof; symbol “b2” is connected to a gate of the PMOS transistor pa2, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c1” is connected to a drain thereof; symbol “b1” is connected to a gate of the NMOS transistor nb1, symbol “b3” is connected to a source thereof, and symbol “c1” is connected to a drain thereof; symbol “b2” is connected to a gate of the NMOS transistor nb2, symbol “vss (ground potential)” is connected to a source thereof, and symbol “b3” is connected to a drain thereof; symbol “c1” is connected to a gate of the PMOS transistor pc1, symbol “vdd (supply potential)” is connected to a source thereof, and symbol “c2” is connected to a drain thereof; and symbol “c1” is connected to a gate of the NMOS transistor nc1, symbol “vss (ground potential)” is connected to a source thereof, and symbol “c2” is connected to a drain thereof. It should be understood that connection portions of the respective nodes are indicated by fly lines.
FIG. 29 is a structural diagram obtained during a layout process. In FIG. 29, symbol “IL1” shows a 2-input NOR, symbols “a1” and “a2” indicate inputs, and symbol “b1” represents an output. In the transistor level, the 2-input NOR IL1 is arranged by PMOS transistors pa1, pa2, and NMOS transistors na1, na2. Symbol “IL2” shows a 2-input NAND, symbols “b1” and “b2” indicate inputs, and symbol “c1” represents an output. In the transistor level, the 2-input NAND IL2 is arranged by PMOS transistors pb1, pb2, and NMOS transistors nb1, nb2. Symbol “IL3” shows an inverter, symbol indicates an input, and symbol “c2” represents an output. In the transistor level, the inverter IL3 is arranged by a PMOS transistor pc1, and an NMOS transistor nc1. It should also be understood that connection portions of the respective nodes are represented by fly lines.
FIG. 30 is a layout structural diagram obtained after the layout process has been accomplished. In FIG. 30, in the 2-input NOR, symbols “a1” and “a2” are inputs, and symbol “b1” shows an output; in the 2-input NAND, symbols “b1” and “b2” are inputs, and symbol “c1” shows an output; and in the inverter, symbol “c1” represents an input, and symbol “c2” shows an output.
FIG. 31 to FIG. 33 show an example of sub-circuits which are contained in the circuit of FIG. 26. FIG. 31 is a structural diagram of a 2-input NOR, (1) represents a mask pattern, (2) shows a circuit diagram of a gate level, and (3) indicates a circuit diagram of a transistor level. FIG. 32 is a structural diagram of a 2-input NAND, (1) represents a mask pattern, (2) shows a circuit diagram of a gate level, and (3) indicates a circuit diagram of a transistor level. FIG. 33 is a structural diagram of an inverter, (1) represents a mask pattern, (2) shows a circuit diagram of a gate level, and (3) indicates a circuit diagram of a transistor level.
In the method executed in the conventional semiconductor designing apparatus, such a layout as shown in FIG. 30 is constructed by editing the circuit diagram of the gate level shown in FIG. 26 to obtain the circuit of the transistor level indicated in FIG. 27 by the circuit editing unit 3. Otherwise, the designing operation is carried out from the circuit diagram of the transistor level shown in FIG. 27, data is supplied to the layout editing unit 5, and the layout of the transistor level indicated in FIG. 28 is rearranged to obtain the layout as represented in FIG. 30 in such a manner that arranging operations and wiring operations are semi-automatically carried out every element.
Next, a description is made of operations of the conventional semiconductor designing apparatus with employment of the above-explained arrangement. First, a circuit diagram entered from the input unit 1 of FIG. 25 is selected by the CPU 2. At this time, the CPU 2 enters the circuit diagram information inputted from the input unit 1 into the circuit editing unit 3. Next, this circuit diagram information is edited by the circuit editing unit 3 in response to an editing instruction entered from the input unit 1, and then, the edited circuit diagram is stored in the circuit diagram database 4. Next, layout information entered from the input unit 1 is inputted to the layout editing unit 5. Subsequently, this layout information is edited by the layout editing unit 5 in accordance with an editing instruction entered from the input unit 1, and then the edited layout information is stored in the layout database 6. At this time, in such a case that a design rule judging instruction is entered from the input unit 1, the design rule control unit 7 performs a check of a design rule as to the layout edited by the layout editing unit 5. Also, in such a case that a connection extracting portion instruction is entered from the input unit 1, the connection extracting unit 8 extracts both the circuit data of the circuit editing unit 3 and the connection information of the layout data of the layout editing unit 5. As a result, the circuit diagram information, the layout information, the check result of the design rule, and the connection extraction result are outputted from the output unit 9.
It should be noted that the conventional layout designing operation has been performed by way of the polygon layout (for example, refer to “That's understood, Electronic Designing EDA (P. 125) Polygon Editor” special issue, Japanese magazine NIKKEI ELECTRONICS (10-14) 1996).
However, in the above-described conventional semiconductor designing apparatus, there are the below-mentioned problems:    (1). The internal portions of the structural elements contained in the circuits must be arranged and must be wired. Even in the case that the circuits having the same structures are used, the internal portions of the structural elements must be repeatedly arranged and wired every time the circuit is used, which cause that the designing time period is prolonged.    (2). In such a case that the structures of the structural elements are determined, the internal shapes of the structural elements cannot be changed.    (3). Since the attributes of the elements cannot be changed, a degree of freedom as to the layout is restricted.    (4). Since instances cannot be added to the elements, substrate contacts and the like cannot be inputted which do not depend upon the circuit diagrams.    (5). The layout designing operations cannot be commenced until the circuit diagram are determined.    (6). The net names and the instance names of the circuits and the layouts are not made coincident with each other, so that debugging operations become difficult.    (7). The different points between the circuits and the layouts cannot be readily retrieved, so that debugging operations become difficult.    (8). The inputs which should be prohibited cannot be avoided in advance, so that erroneous designing operations occur.    (9). Since the layout data can be hardly recognized by any persons other than persons who have well skilled in the art, lengthy time is necessarily required in order to get acquainted with the layouts.    (10). Although various sorts of shapes are prepared in order to realize the layout data having the functions, layouts cannot be freely selected in order to be adapted to characteristics of design portions.    (11). Since the design rules have not yet been determined, the layout designing operations cannot be commenced.    (12). In such a case that data whose function has not yet been firmed is entered, the layout designing operation cannot be carried out.    (13). In the case that temporal data is formed by employing data whose function has not yet been firmed, this temporal data cannot be reused.    (14). When the circuits are edited, only the data about the circuits are merely displayed. Also, when the layouts are edited, only the data about the layouts are merely displayed. As a result, mutual recognizing characteristics between the circuits and the layouts are deteriorated.    (15). The portions which are not changed cannot be designated, so that erroneous corrections may be made.    (16). Since comments which bridge the circuits and the layouts cannot be made up, the designing information cannot be sufficiently transferred between the circuit designers and the layout designers.    (17). Since the layouts cannot be prepared which are adapted to the designed wiring layers, the layout must be formed every designed wiring layers, which requires a large number of designing steps.    (18). Since the design data must be formed every process, even when similar circuits are designed, the design data cannot be applied to different processes.